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| 1. general description the TEA1753LT is the third generation of green switched mode power supply (smps) controller ics. the TEA1753LT combines a controller for power factor correction (pfc) and a flyback controller. its high level of integration allows the design of a cost-effective power supply with a very low number of external components. the special built-in green func tions provide high efficiency at all power levels. this efficiency applies to quasi-resonant operation at high-power levels, quasi-resonant operation with valley skipping, as well as to reduced frequency operation at lower power levels. at low-power levels , the pfc switches off to maintain high efficiency. during low-power conditions, the flyback controller sw itches to frequency reduction mode and limits the peak current to an adjustable minimum value. this mode ensures high efficiency at low-power and good standby pow er performance while minimizing audible noise from the transformer. the controller can be switched to the power-down mode for no-load operation. in this mode, the controller is shut down fo r very low standby power applications the TEA1753LT is a multi-chip module (mcm), containing 2 chips. the proprietary high-voltage bcd800 process which makes dire ct start-up possible from the rectified universal mains voltage in an effective and green way. the second low voltage silicon on insulator (soi) is used for accura te, high-speed protec tion functions and control. the TEA1753LT enables the design of highly efficient and reliable supplies with power requirements of up to 250 w using a minimum number of external components. remark: all values provided throughout the running text, are typical values unless otherwise stated. TEA1753LT hv start-up dcm/qr flyback c ontroller with integrated dcm/qr pfc controller rev. 3 ? 24 august 2012 product data sheet
TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 2 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller 2. features and benefits 2.1 distinctive features ? integrated pfc and flyback controller ? universal mains supply oper ation (70 v (ac) to 276 v (ac)) ? dual-boost pfc with accurate maximum output voltage (nxp patented) ? high level of integration, re sulting in a very low external component count and a cost-effective design ? adjustable pfc switch-off delay 2.2 green features ? on-chip start-up current source ? power down functionality for very low standby power 2.3 pfc green features ? valley/zero voltage switching (zvs) for minimum switching losses (nxp patented) ? frequency limitation to reduce switching losses ? pfc is switched off when a low load is detected at the flyback output 2.4 flyback green features ? valley switching for minimum switching losses (nxp patented) ? frequency reduction with adjustable minimum peak current at low-power operation to maintain high efficiency at low output power levels 2.5 protection features ? safe restart mode for system fault conditions ? continuous mode protection with demagnetiz ation detection for both converters (nxp patented) ? undervoltage protection (uvp) (foldback during overload) ? accurate overvoltage protection (ovp) for both converters (adjustable for flyback converter) ? mains voltage independent overpower protection (opp) ? open control loop protection for both converters. the open-loop protection on the flyback converter is latched ? overtemperature protection (otp) ? low and adjustable overcurrent protection (ocp) trip level for both converters ? general-purpose latched protection input for system overtemperature protection (otp) for example 3. applications ? the device is used in all applications requiring an efficient and cost-effective power supply solution up to 250 w. notebook adapters, in particular, benefit from the high level of integration TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 3 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller 4. ordering information table 1. ordering information type number package name description version TEA1753LT so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 4 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller 5. block diagram fig 1. block diagram ! "#$ " % &" ' ( ) * ' + ,- .- ,- /-, '01 2"$ 2"$ "3 4'5 ' ' "6$7#"8 " & & "& $" "#$ 9 $:: $"7 $"% ' "6$7#"8 "#$6$7#"8 "#$6$7#"8 * ' + 9 (*'+ ' %"2 6;37 3 2"$ %<3 6$7#"8 ! 6$7#"8&" /, /. ! &" '10 "& ' ( ) "$ 3$7 =1 5 ' = 1 5 ' 6$7#"8 &" *'1 0 * 1 6$7#"8 .- > ? // @ a 4 /? / 5 ) . / * ' 4 @ % ) *) "3 1 1 @ ' ? ' . ' .-a $"% 6;37 3 /-, 6$7#"8 ! ,- .- '1 ' 3"$# 3"$ # 3"$ # $: : : %"2 : : : : 1 , $:: $"7 $:: / ) '( ? ' . ' 6$7#"8 2"$ $" '4) $"% $"% ' $: : $:: $"7 '/>.%<3 '/>. %<3 $: 1 ! ! ' TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 5 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin configuration: TEA1753LT (sot109-1) TEA1753LT v cc hv gnd hvs fbctrl pfctimer fbaux fbdriver latch pfcdriver pfccomp pfcsense vinsense fbsense pfcaux vosense 001aan785 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 table 2. pin description symbol pin description v cc 1 supply voltage gnd 2 ground fbctrl 3 flyback control input fbaux 4 auxiliary winding input for demagnetization timing and flyback ovp latch 5 general-purpose protection input pfccomp 6 frequency compensation pin for pfc vinsense 7 mains voltage sense input pfcaux 8 auxiliary winding input for demagnetization timing for pfc vosense 9 sense input for pfc output voltage fbsense 10 flyback current sense input pfcsense 11 pfc current sense input pfcdriver 12 pfc gate-driver output fbdriver 13 flyback gate-driver output pfctimer 14 delay timer pin for pfc on/off control hvs 15 high-voltage safety spacer, not connected hv 16 high-voltage start-up/ flyback valley sensing TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 6 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller 7. functional description 7.1 general control the TEA1753LT contains a controller for a powe r factor correction circuit as well as a controller for a flyback circuit. a typical configuration is shown in figure 3 . 7.1.1 start-up and undervoltage lockout (uvlo) initially the capacitor on the v cc pin is charged from the high-voltage mains using the hv pin. when v cc is less than v trip , the charge current is low. this low current protects the ic if the v cc pin is shorted to ground. to ensure a s hort start-up time, the charge current above v trip is increased until v cc reaches v th(uvlo) . when v cc is between v th(uvlo) and v startup , the charge current return s to low to ensure a low safe restart duty cycle during fault conditions. the control logic activates the internal circui try and switches off the hv charge current when the voltage on pin v cc passes the v startup level. first, the latch pin current source is activated and the soft-start capacito rs on the pfcsense and fbsense pins are charged. also the clamp circuit on the pfccomp pin is activated. the pfc circuit is activated when the following conditions are met: ? the latch pin voltage exceeds the v en(latch) voltage ? the pfccomp pin voltage reaches the v en(pfccomp) voltage ? the soft-start capacitor on the pfcsense pin is charged fig 3. TEA1753LT ic typical configuration /, // a /? /. @ ? > . , / / / TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 7 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller if the soft start capacitor on the fbsense pin is charged, the flyba ck converter is also activated. the flyback converter output voltage is then regulated to its nominal output voltage. the auxiliary winding of the flyba ck converter takes over the ic supply. see figure 4 . if during start-up the latch pin does not reach the v en(latch) level before v cc reaches v th(uvlo) , it is deactivated. the charge cu rrent is then switched on again. when the flyback co nverter starts, v fbctrl is monitored. if this output voltage does not reach its intended regulation level within a specified time, the voltage on the fbctrl pin reaches the v to(fbctrl) level. an error is then assumed and a latched protection is initiated. when one of the protection functions is activa ted, both converters stop switching and the v cc voltage drops to v th(uvlo) . a latched protection recharges capacitor c vcc using the hv pin, but does not restart the converters. to provide safe restart protection, the capacitor is recharged using the hv pin and the device restarts (see block diagram, figure 1 ). if ovp of the pfc circuit (v vosense >v ovp(vosense)) occurs, the pfc controller stops switching until the vosense pin voltage drops to less than v ovp(vosense) . if a mains undervoltage is detected, v vinsense TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 8 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller 7.1.2 power down the power-down mode is activated for very low standby power applications by pulling the vinsense pin below the v th(pd) level. the TEA1753LT stops switching and the safe restart protection is activated. the high-volt age start-up current source is also disabled during power-down, so the TEA1753LT does no t restart until the vinsense pin voltage is raised again. during power down all internal circuitry is disabled except for a voltage detection circuit on the vinsense pin. this ci rcuit is supplied by the hv pin and draws 16 ? a from the hv pin for biasing. if the vinsense pin is pulled low, a latched protection is also reset. (see section 7.1.5 ) fig 4. start-up sequence, normal operation and restart sequence v cc latch protection pfcsense pfcdriver fbsense fbdriver fbctrl vosense v o charging vcc capacitor starting converters normal operation protection restart soft start soft start i hv v start(vinsense) v to(fbctrl) v startup v th(uvlo) v trip v en(la tch) v start(fb) vinsense 014aaa744 pfccomp v en(pfccomp) TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 9 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller 7.1.3 supply management all internal reference voltages are derived from a temperature compensated and trimmed on-chip band gap circuit. internal reference currents are derived from a temperature compensated and trimmed on-chip current reference circuit. 7.1.4 latch input the latch pin is a general-purpose input pin, wh ich is used to switch off both converters. the pin sources a current i o(latch) of 80 ? a. switching is stopped as soon as the voltage on this pin drops below 1.25 v. at initial start-up, switching is inhibited un til the capacitor on the latch pin is charged above 1.35 v. no internal filtering is done on this pin. an internal zener clamp of 2.9 v protects this pin from excessive voltages. 7.1.5 fast latch reset in a typical application, the ma ins is interrupted briefly to reset the latched protection. the pfc bus capacitor, c bus , does not have to discharge for this latched protection to reset. when the vinsense voltage drops below 750 mv and is then raised to 870 mv, the latched protection is reset. the latched protection is also reset by removing the voltage on the v cc and hv pins. 7.1.6 overtemperature protection an accurate internal temperature protection is provided in the circuit. when the junction temperature exceeds the thermal shut-down temp erature, the ic stops switching. as long as otp is active, the capacitor c vcc is not recharged from the hv mains. if the v cc supply voltage is not sufficient, the otp circuit is supplied from the hv pin. otp is a latched protection. it is reset by removing the voltage on the v cc and hv pins or by the fast latch reset function. (see section 7.1.5 ) 7.2 power factor correction circuit the power factor correction circuit oper ates in quasi-resonant or discontinuous conduction mode (cdm) with valley switching. the next primary stroke is only started when the previous secondary stroke has ended and the voltage across the pfc mosfet has reached a minimum value. v pfcaux is used to detect transformer demagnetization and the minimum voltage across the external pfc mosfet switch. 7.2.1 t on control the power factor correction circuit is operated in t on control. the resulting mains harmonic reduction is well within t he class-d requirements. 7.2.2 valley switching and demagnetization (pfcaux pin) the pfc mosfet is switched on after the trans former is demagnetized. internal circuitry connected to the pfcaux pin detects the end of the secondary stroke. it also detects the voltage across the pfc mosfet. to reduce switching losses and electromagnetic interference (emi) (valley switching), the next stroke is started if the voltage across the pfc mosfet is at its minimum. TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 10 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller if a demagnetization signal is not detected on the pfcaux pin, the controller generates a zero current signal (zcs), 50 ? s after the last pfcgate signal. if a valley signal is not detected on the pf caux pin, the controller generates a valley signal 4 ? s after demagnetization is detected. to protect the internal circuitry during lightning events, for example, add a 5 k ? series resistor to pfcaux. to prevent incorrect switching due to external disturbance, place the resistor close to the ic on the printed-circuit board. 7.2.3 frequency limitation to optimize the transformer and minimize s witching losses, the s witching frequency is limited to f sw(pfc)max . if the frequency for quasi-res onant operation is above the f sw(pfc)max limit, the system switches over to dcm. th e pfc mosfet is only switched on at a minimum voltage across the s witch (valley switching). 7.2.4 mains voltage compensation (vinsense pin) the equation for the transfer function of a power factor corrector contains the square of the mains input voltage. in a typical applic ation this results in a low bandwidth for low mains input voltages and a high band width for high mains input voltages . to compensate for the mains input voltage influence, TEA1753LT contains a correction circuit. the average input voltage is measured using the vinsense pin and the information is fed to an internal compensati on circuit. using this compensation, it is possible to keep the regulation loop bandwidth constant over the mains input range. this yields a fast transient response on load st eps, while still complying with class-d mhr requirements. in a typical application, a resistor and two capacitors on the pfccomp pin set the bandwidth of the regulation loop. 7.2.5 soft start-up (pfcsense pin) to prevent audible transformer noise at start-up or during hiccup, the soft-start function slowly increases the transformer peak current. this increase is achi eved by inserting r ss1 and c ss1 between the pfcsense pin and current sense resistor r sense1 . an internal current source charges the capacitor to: (1) the voltage is limited to v start(soft)pfc . the start level and the time constant of the increasing primary current level is adjusted externally by changing the values of r ss1 and c ss1 . (2) the charging current i start(soft)pfc flows as long as v pfcsense is below 0.5 v. if v pfcsense exceeds 0.5 v, the soft-start curren t source starts limiting current i start(soft)pfc . when the pfc starts switching, the i start(soft)pfc current source is switched off; see figure 5 . v pfcsense i start soft ?? pfc r ss1 ? = ? soft s ? tart 3 r ss1 c ss1 ?? = TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 11 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller 7.2.6 low-power mode when the output power of the flyback converter (see section 7.3 ) is low, the flyback converter switches over to frequency modulation mode. when the maximum switching frequency of the flyback drops below 48 khz, the power factor correction circuit is switched off to maintain high efficiency. connect a capacitor to th e pfctimer pin to delay switching off (see also section 7.2.7 ). during low-power mode operation, the pfccomp pin is clamped to a minimum voltage of 3.5 v or 2.5 v and a maximum voltage of 3.9 v. the lower clamp voltage depends on the voltage on vinsense pin. this voltage limit s the maximum power that is delivered when the pfc is switched on again. the upper clamp voltage ensures that the pfc returns from low-power mode to its normal regulation point in a limited time. when the maximum switching frequency of the flyback converter exceeds 86 khz, the power factor correction circuit restores normal operation. 7.2.7 pfc off delay (pin pfctimer) when the flyback converter maximum frequency drops below 48 khz, the pfc is switched off. the ic then outputs a 5 ? a current to the pfctimer pin. when the voltage on the pfctimer pin reaches 3.6 v, the pfc is switched off by performing a soft-stop. when the flyback converter frequency exceeds 86 khz, a switch discharges the pfctimer pin capacitor. when the voltage on the pctimer pin drops below 1.27 v, the pfc is switched on (see figure 6 ). fig 5. soft-start-up of pfc fig 6. pfc start/stop via ppfctimer pin r s q 1.27 v low power delay (pfc on) 3.6 v 5 a 14 pfctimer low power 014aaa740 TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 12 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller 7.2.8 dual-boost pfc the mains input voltage modulates the pfc output voltage. the mains input voltage is measured using the vinsense pin. if the voltage on the vinsense pin drops below 2.2 v, the current is sourced from the vosense pin. to ensure the stable switch-over, a 200 mv transition region is inserted around the 2.2 v, see figure 7 . for low vinsense input voltag es, the output current is 8 ? a. this output current, in combination with the resistors on the vosense pin, sets the lower pfc output voltage level at low mains voltages. at high mains input voltages, the current is swit ched to zero. the pfc output voltage is then at its maximum. as this current is zero in this situation, it does not affect the accuracy of the pfc output voltage. for proper switch-off, the vosense current is switched to its maximum value of 8 ? a when the voltage on pin vosense drops below 2.1 v. 7.2.9 overcurrent protection (pfcsense pin) the maximum peak current is limited cycle-by-c ycle by sensing the voltage across an external sense resistor, r sense1 , on the source of the external mosfet. the voltage is measured using the pfcsense pin. 7.2.10 mains undervoltage lockout/brownout protection (vinsense pin) to prevent the pfc from operating at very low mains input voltages, the voltage on the vinsense pin is continuously sensed. when the voltage on this pin drops below the v stop(vinsense) level, switching of the pfc is stopped. 7.2.11 overvoltage protection (vosense pin) to prevent output overvoltage during load steps and mains transients, an overvoltage protection circuit is built in. when the voltage on the vosense pin exceeds the v ovp(vosense) level, switching of the power factor correction circuit is inhibited. switching of the pfc recommences when the vosense pin voltage drops below the v ovp(vosense) level again. when the resistor between the vosense pi n and ground is open, the overvoltage protection is also triggered. fig 7. voltage to current transfer function for dual boost pfc v vinsense i i(vosense) 014aaa097 ?8 a 2.2 v TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 13 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller 7.2.12 pfc open-loop protection (vosense pin) the power factor correction circuit does not start switching until the voltage on the vosense pin is above the v th(ol)(vosense) level. this feature protects the circuit from open-loop and vosense short-circuit. 7.2.13 driver (pfcdriver pin) the driver circuit to the gate of the power mosfet has a current so urcing capability of ? 500 ma and a current sink capa bility of 1.2 a. these capabilit ies permit fast turn-on and turn-off of the power mosfet for efficient operation. 7.3 flyback controller the TEA1753LT includes a controller for a flyback converter. the flyback converter operates in quasi-reso nant or dcm with valley switchin g. the auxiliary winding of the flyback transformer provides demagnetization de tection and powers the ic after start-up. 7.3.1 multimode operation the TEA1753LT flyback controller operates in several modes; see figure 8 . at high output power the co nverter switches to quasi-resonant mode. the next converter stroke starts after demagnetization of the transformer and detection of the valley. in quasi-resonant mode switching losses are minimi zed. this minimization is achieved by the converter only switching on when the voltag e across the external mosfet is at its minimum (see also section 7.3.2 ). to prevent high frequency operation at low loads, the maximum s witching frequency is limited to 125 khz. when the frequency limit is reached, the quasi-resonant operation changes to dcm with valley skipping. this mo de limits the mosfet switch-on losses and conducted emi. fig 8. multimode operation flyback discontinuous with valley switching quasi-resonant pfc off frequency reduction output power flyback switching frequency 014aaa745 pfc on 86 khz 48 khz 125 khz i pmin adjust TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 14 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller a voltage controlled oscillator (vco) contro ls the frequency at very low power and standby levels. the minimum frequency is reduced to zero. during frequency reduction mode, the primary peak current is kept at an adjustable minimal level to maintain a high efficiency. as the primary peak current is low in frequency reduction operation, no audible noise is noticeable at switching frequencies in the audible range. valley switching is also active in this mode. in frequency reduction mode, the pfc controller is switched off. the flyback maximum frequency changes linearly with the control voltage on the fbctrl pin (see figure 9 ). hysteresis has been added for stable on and off switching of the pfc. at no-load operation, the switching frequency is reduced to (almost) zero. the input voltage of the flyback converter and the capacitance on the drain node of the flyback power switch affect the frequency reduction slope. by choosing the proper compensation, the frequency reduction slope for high input voltages is chosen as the same as for low input voltages. this compensation yields an input voltage independent pfc switch-on and switch-off power leve l (see the application information in section 11 ). 7.3.2 valley switching (hv pin) a new cycle starts when the exte rnal mosfet is switched on. v fbsense and v fbctrl determine the on-time. the mosfet is then switched off and the secondary stroke starts. after the secondary stroke, the drain volta ge shows an oscillation with a frequency of approximately: (3) where l p is the primary self-inductance of the flyback transformer and c d is the capacitance on the drain node. when the internal oscillator voltage is high and the secondary stroke ended, the circuit waits for the lowest drain voltage before starting a new primary stroke. fig 9. frequency control of flyback v fbctrl 1.5 v discontinuous with valley switching quasi-resonant frequency reduction pfc off flyback switching frequency 014aaa746 pfc on f sw(fb)max f 1 2 ?? l p c d ? ?? ? ?? -------------------------------------------------- - = TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 15 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller figure 10 shows the drain voltage, valley signal, se condary stroke signal and the internal oscillator signal. valley switching allows high frequency operat ion as capacitive switching losses are reduced, see equation 4 . high frequency operation makes small and cost-effective magnetic components possible. (4) 7.3.3 current mode control (fbsense pin) current mode control is used for the flyb ack converter for its good line regulation. the fbsense pin senses the primary current across an external resist or and compares it with an internal control voltage. the internal control voltage is proportional to the fbctrl pin voltage, see figure 11 . the fbsense pin output s a current of 3 ? a. this current runs through the resistors from the fbsense pin to the sense resistor and cr eates an offset volt age. the minimum peak current of the flyback is adjusted using this offset voltage. adjusting the minimum peak current level, changes the frequency reduction slope (see figure 8 ). (1) start of new cycle at lowest drain voltage. (2) start of new cycle in a cl assical pulse width modulation (pwm) system without valley detection. fig 10. signals for valley switching p 1 2 -- - c d v 2 ? f ?? = drain secondary stroke 014aaa027 secondary ringing primary stroke valley (2) (1) secondary stroke oscillator TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 16 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller the driver output is latched in the logic, preventing multiple switch-on. 7.3.4 demagnetization (fbaux pin) the system is always in qr or dcm. the internal oscillator does not start a new primary stroke until the previous secondary stroke has ended. demagnetization features a cycl e-by-cycle output short-circuit protection by immediately lowering the frequency (longer off-ti me), thus reducing the power level. demagnetization recognition is suppressed during the first t sup(xfmr_ring) time of 2 ? s. this suppression is necessary at low output voltages and at start-up. it is also required in applications where the transformer has a large leakage inductance. if the fbaux pin is open-circuit or not connec ted, a fault condition is assumed and the converter immediately stops. operation restarts as soon as the fault condition is removed. 7.3.5 flyback control/time-out (fbctrl pin) the fbctrl pin is connected to an internal voltage source of 3.5 v using an internal resistor of 3 k ? . when the voltage on this pin exceeds 2.5 v, the connection is disabled and the pin is biased with a small current. if th e voltage on this pin exceeds 4.5 v, a fault is assumed, switching is stopped and a latched protection is activated. if a capacitor and a resistor are connected in se ries to this pin, a time-out function is created to protect against an open control loop. see figure 12 and figure 13 . the time-out function is disabled by connecting a resistor (100 k ? ) to ground on the fbctrl pin. if the pin is short-circuited to ground, swit ching of the flyback controller is prevented. during normal operating conditions, the co nverter regulates the output voltage. the voltage on the fbctrl pin is then between 1.3 v for the minimum output power and 2 v for the maximum output power . fig 11. peak current control of flyback v fbctrl 1.5 v 2.0 v 0.65 v flyback frequency reduction pfc off fbsense peak voltage 014aaa747 pfc on flyback discontinuous or qr flyback cycle skip mode sense resistor peak voltage fbsense offset voltage v sense(fb)max 0.325 v TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 17 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller 7.3.6 soft start-up (fbsense pin) to prevent audible transformer noise during start-up, the soft-start function slowly increases the transformer peak current. this in crease is achieved by inserting a resistor and a capacitor between pin 10 (fbsense) and the cu rrent sense resistor. an internal current source charges the capacitor to: (5) with a maximum of approximately 0.63 v. the start level and the time constant of the increasing primary current level is adjusted externally by changing the values of r ss2 and c ss2 . (6) the soft-start current i start(soft)fb is switched on as soon as v cc reaches v startup . when v fbsense has reached 0.63 v, the flyback converter starts switching. fig 12. time-out protection circuit fig 13. latched time-out protection (signals) in the TEA1753LT 014aaa049 fbctrl 2.5 v 4.5 v 30 a 3 k 3.5 v time-out 014aaa298 4.5 v 2.5 v v fbctrl output voltage intended output voltage not reached within time? out time. latched vi start soft ?? fb r ss2 ? = ? soft s ? tart 3 r ss1 c ss1 ?? = TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 18 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller the charging current i start(soft)(fb) flows as long as v fbsense is less than approximately 0.63 v. if v fbsense exceeds 0.63 v, the soft start curren t source starts limiting the current. after the flyback converter has started, the soft-start current source is switched off. 7.3.7 maximum on-time the flyback controller limits the on-time of the external mosfet to 40 ? s. when the on-time is longer than 40 ? s, the ic stops switching and enters the safe restart mode. 7.3.8 overvoltage protection (fbaux pin) an output overvoltage protection is impl emented in the greenchip iii series. in the TEA1753LT, the auxiliary voltag e is sensed using the curren t flowing into the fbaux pin during the secondary stroke. th e auxiliary winding voltage is a well-defined r eplica of the output voltage. an internal f ilter averages voltage spikes. an internal up-down counter prevents false ovp detection which occurs during esd or lightning events. the internal counter counts up by one when the output voltage exceeds the ovp trip level within one switching cycl e. the internal counter counts down by two when the output voltage has not exceeded the ovp trip level within one switching cycle. when the counter has reached eight, the ic assumes a true ovp, sets the latched protection and switches off both converters . the converter only restarts after the ovp latch is reset . in a typical application, the internal latch is reset when the vinsense voltage drops below 750 mv and is then raised to 870 mv. the latched protection is also reset by removing both the voltage on the vcc and hv pins. the demagnetization resistor, r fbaux sets the output voltage v o(ovp) at which the ovp function trips: (7) where n s is the number of secondary turns and n aux is the number of au xiliary turns of the transformer. current i ovp(fbaux) is internally trimmed. fig 14. soft start-up of flyback. < ' / * , , , , . ' $!$ " 6 6# b? ' v oovp ?? n s n aux ---------- - i ovp fbaux ?? r fbaux v clamp fbaux ?? + ? ?? = TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 19 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller accurate ovp detection is made po ssible by adjusting the value of r fbaux to the turns ratio of the transformer. 7.3.9 overcurrent protection (fbsense pin) the primary peak current in the transformer is measured accurately cycle-by-cycle using the external sense resistor r sense2 . the ocp circuit limits v fbsense to a level set by v fbctrl (see also section 7.3.3 ). the ocp detection is suppressed during the leading-edge blanking period, t leb , to prevent false triggering due to switch-on spikes. 7.3.10 overpower protection during the primary stroke of the flyback converter, the input voltage is measured by sensing the current that is drawn from the fbaux pin. the current information is used to limit the maximum peak current of the flyback converter, measured from the fbsense pin. the internal compensati on is such, that a maximum output power is realized which is almost independent of the input voltage. the opp curve is given in figure 16 . 7.3.11 driver (fbdriver pin) the driver circuit to the po wer mosfet gate has a curr ent sourcing capability of ? 500 ma and a current sink capability of 1.2 a. these capabilities permit fast switching of the power mosfet for efficient operation. fig 15. ocp leading edge blanking t leb ocp level v fbsense t 014aaa022 fig 16. overpower protection curve ?360 0 ?100 014aaa749 0.65 0.46 i fbaux (a) v fbsense (v) TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 20 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller 8. limiting values table 3. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit voltages v cc supply voltage ? 0.4 +38 v v latch voltage on the latch pin current limited ? 0.4 +5 v v fbctrl voltage on the fbctrl pin ? 0.4 +5 v v pfccomp voltage on the pfccomp pin ? 0.4 +5 v v vinsense voltage on the vinsense pin ? 0.4 +5 v v vosense voltage on the vosense pin ? 0.4 +5 v v pfcaux voltage on the pfcaux pin ? 25 +25 v v fbsense voltage on the fbsense pin current limited ? 0.4 +5 v v pfcsense voltage on the pfcsense pin current limited ? 0.4 +5 v v pfctimer voltage on the pfctimer pin ? 0.4 +5.5 v v hv voltage on the hv pin ? 0.4 +650 v currents i fbctrl current on the fbctrl pin ? 30 ma i fbaux current on the fbaux pin ? 1+1ma i pfcsense current on the pfcsense pin ? 1+10ma i fbsense current on the fbsense pin ? 1+10ma i fbdriver current on the fbdriver pin duty cycle < 10 ?? 0.8 +2 a i pfcdriver current on the pfcdriver pin duty cycle < 10 ?? 0.8 +2 a i hv current on the hv pin - 8 ma general p tot total power dissipation t amb <75 ? c-0 . 6w t stg storage temperature ? 55 +150 ?c t j junction temperature ? 40 +150 ?c esd v esd electrostatic discharge voltage class 1 human body model pins 1 to 13 [1] -2000v pin 16 (hv) [1] -1500v machine model [2] -200v charged device model -500v TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 21 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller [1] equivalent to discharging a 100 pf capacitor through a 1.5 k ? series resistor. [2] equivalent to discharging a 200 pf capacitor through a 0.75 ? h coil and a 10 ? resistor. 9. thermal characteristics 10. characteristics table 4. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air; jedec test board 124 k/w r th(j-c) thermal resistance from junction to case in free air; jedec test board 37 k/w table 5. characteristics t amb =25 ? c; v cc = 20 v; all voltages are measured with respect to ground; currents are positive when flowing into the ic; unless otherwise specified. symbol parameter conditions min typ max unit start-up current source (hv pin) i hv current on the hv pin v hv >80v v cc TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 23 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller i prot(pfcsense) protection current on the pfcsense pin ? 50 - ? 5na soft-start pfc (pfcsense pin) i start(soft)pfc pfc soft-start current ? 75 ? 60 ? 45 ? a v start(soft)pfc pfc soft-start voltage enabling voltage 0.46 0.50 0.54 v v stop(soft)pfc pfc soft-stop voltage disabling voltage 0.42 0.45 0.48 v oscillator pfc f sw(pfc)max maximum pfc switching frequency -250-khz t off(pfc)min minimum pfc off-time 0.8 1.1 1.4 ? s valley switching pfc (pfcaux pin) (? v/ ? t) vrec(pfc) pfc valley recognition voltage change with time --1.7v/ ? s t vrec(pfc) pfc valley recognition time v pfcaux = 1 v peak to peak [2] --300ns demagnetization to ? v/ ? t=0 [3] --50ns t to(vrec)pfc pfc valley recognition time-out time 346? s demagnetization management pfc (pfcaux pin) v th(comp)pfcaux comparator threshold voltage on the pfcaux pin ? 150 ? 100 ? 50 mv t to(demag)pfc pfc demagnetization time-out time 40 50 60 ? s i prot(pfcaux) protection current on the pfcaux pin v pfcaux =50mv ? 75 - ? 5na pfc off delay (pfctimer pin) i source(pfctimer) source current on the pfctimer pin - ? 5- ? a i sink(pfctimer) sink current on the pfctimer pin v pfctimer = 5 v - 3.5 - ma v start(pfctimer) start voltage on the pfctimer pin -1.27-v v stop(pfctimer) stop voltage on the pfctimer pin -3.6-v driver (pfcdriver pin) i src(pfcdriver) source current on the pfcdriver pin v pfcdriver =2v - ? 0.5 - a i sink(pfcdriver) sink current on the pfcdriver pin v pfcdriver =2v - 0.7 - a v pfcdriver =10v -1.2-a v o(pfcdriver)max maximum output voltage on the pfcdriver pin 9.5 10.8 12 v overvoltage protection flyback (fbaux pin) i ovp(fbaux) overvoltage protection current on the fbaux pin 279 300 321 ? a table 5. characteristics ?continued t amb =25 ? c; v cc = 20 v; all voltages are measured with respect to ground; currents are positive when flowing into the ic; unless otherwise specified. symbol parameter conditions min typ max unit TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 24 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller n cy(ovp) number of overvoltage protection cycles 6812 demagnetization management flyback (fbaux pin) v th(comp)fbaux comparator threshold voltage on the fbaux pin 60 80 110 mv i prot(fbaux) protection current on the fbaux pin v fbaux =50mv ? 75 - ? 5na v clamp(fbaux) clamp voltage on the fbaux pin i fbaux = ? 100 ? a ? 0.85 ? 0.7 ? 0.55 v i fbaux =300 ? a 0.79 0.94 1.09 v t sup(xfmr_ring) transformer ringing suppression time 1.5 2 2.5 ? s pulse width modulator flyback t on(fb)min minimum flyback on-time - t leb -ns t on(fb)max maximum flyback on-time 32 40 48 ? s oscillator flyback f sw(fb)max maximum flyback switching frequency 100 125 150 khz v start(vco)fbctrl vco start voltage on the fbctrl pin 1.3 1.5 1.7 v f sw(fb)swon(pfc) pfc switch-on flyback switching frequency - 86 - khz f sw(fb)swoff(pfc) pfc switch-off flyback switching frequency - 48 - khz ? v vco(fbctrl) vco voltage difference on the fbctrl pin - ? 0.12 - v peak current control flyback (fbctrl pin) v fbctrl voltage on the fbctrl pin for maximum flyback peak current 1.85 2 2.15 v v to(fbctrl) time-out voltage on the fbctrl pin enable voltage - 2.5 - v trip voltage 4.2 4.5 4.8 v r int(fbctrl) internal resistance on the fbctrl pin -3-k ? i o(fbctrl) output current on the fbctrl pin v fbctrl =0v ? 1.4 ? 1.19 ? 0.93 ma v fbctrl =2v ? 0.6 ? 0.5 ? 0.4 ma i to(fbctrl) time-out current on the fbctrl pin v fbctrl =2.6v ? 36 ? 30 ? 24 ? a v fbctrl =4.1v ? 34.5 ? 28.5 ? 22.5 ? a valley switching flyback (hv pin) (? v/ ? t) vrec(fb) flyback valley recognition voltage change with time ? 75 - +75 v/ ? s t d(vrec-swon) valley recognition to switch on delay time [4] -150-ns soft-start flyback (fbsense pin) i start(soft)fb flyback soft-start current ? 75 ? 60 ? 45 ? a v start(soft)fb flyback soft-start voltage enable voltage 0.55 0.63 0.70 v table 5. characteristics ?continued t amb =25 ? c; v cc = 20 v; all voltages are measured with respect to ground; currents are positive when flowing into the ic; unless otherwise specified. symbol parameter conditions min typ max unit TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 25 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller [1] for a typical application with a compensation network on pin pfccomp, like the example in figure 3 . [2] minimum required voltage change time for valley recognition on pin pfcaux. [3] minimum time required between demagnetization detection and ? v/ ? t = 0 on pin pfcaux. [4] guaranteed by design. overcurrent protection flyback (fbsense pin) v sense(fb)max maximum flyback sense voltage ? v/ ? t=50mv/ ? s 0.61 0.65 0.69 v ? v/ ? t=200mv/ ? s 0.64 0.68 0.72 v sense(fb)min minimum flyback sense voltage ? v/ ? t=50mv/ ? s 0.305 0.325 0.345 v t leb(fb) flyback leading-edge blanking time 255 305 355 ns i adj(fbsense) adjust current on the fbsense pin ? 3.2 ? 3 ? 2.8 ? a overpower protection flyback (fbsense pin) v sense(fb)max maximum flyback sense voltage ? v/ ? t=50mv/ ? s i fbaux =80 ? a 0.61 0.65 0.69 v i fbaux =120 ? a 0.57 0.62 0.67 v i fbaux =240 ? a 0.47 0.52 0.57 v i fbaux =360 ? a 0.41 0.46 0.51 v driver (fbdriver pin) i src(fbdriver) source current on the fbdriver pin v fbdriver =2v - ? 0.5 - a i sink(fbdriver) sink current on the fbdriver pin v fbdriver =2v - 0.7 - a v fbdriver =10v -1.2-a v o(fbdriver)(max) maximum output voltage on the fbdriver pin 9.5 10.8 12 v latch input (latch pin) v prot(latch) protection voltage on the latch pin 1.23 1.25 1.27 v i o(latch) output current on the latch pin v prot(latch) TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 27 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller fig 17. typical application diagram for the TEA1753LT ic /, // a /? /. @ ? > . , / / / '10/ / , , . / 1 TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 28 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller 12. package outline fig 18. package outline sot109-1 (so16) x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot109-1 99-12-27 03-02-19 076e07 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1 TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 29 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller 13. revision history table 6. revision history document id release date data sheet status change notice supersedes TEA1753LT v.3 20120824 product data sheet TEA1753LT v.2 modifications: ? multiple text changes ? multiple graphic updates ? updates to severa l characteristics TEA1753LT v.2 20110408 product data sheet - TEA1753LT v.1 TEA1753LT v.1 20110304 objective data sheet - - TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 30 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller 14. legal information 14.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. 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TEA1753LT all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 3 ? 24 august 2012 31 of 32 nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 14.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. greenchip ? is a trademark of nxp b.v. 15. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors TEA1753LT hv start-up flyback controller with integrated pfc controller ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 24 august 2012 document identifier: TEA1753LT please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 16. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 distinctive features . . . . . . . . . . . . . . . . . . . . . . 2 2.2 green features . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 pfc green features . . . . . . . . . . . . . . . . . . . . . 2 2.4 flyback green features . . . . . . . . . . . . . . . . . . . 2 2.5 protection features . . . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . . 6 7.1 general control . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.1.1 start-up and undervoltage lockout (uvlo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.1.2 power down . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.1.3 supply management. . . . . . . . . . . . . . . . . . . . . 9 7.1.4 latch input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.1.5 fast latch reset . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.1.6 overtemperat ure protection . . . . . . . . . . . . . . . 9 7.2 power factor correction circuit . . . . . . . . . . . . . 9 7.2.1 t on control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.2.2 valley switchin g and demagnetization (pfcaux pin) . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.2.3 frequency limitation . . . . . . . . . . . . . . . . . . . . 10 7.2.4 mains voltage compensation (vinsense pin) . . . . . . . . . . . . . . . . . . . . . . . 10 7.2.5 soft start-up (pfcsense pin) . . . . . . . . . . . . . . . . . . . . . . 10 7.2.6 low-power mode . . . . . . . . . . . . . . . . . . . . . . 11 7.2.7 pfc off delay (pin pfctimer) . . . . . . . . . . . . . . . . . . . . . . . 11 7.2.8 dual-boost pfc . . . . . . . . . . . . . . . . . . . . . . . 12 7.2.9 overcurr ent protection (pfcsense pin) . . . . . . . . . . . . . . . . . . . . . . 12 7.2.10 mains undervoltage lockout/brownout protection (vinsense pin) . . . . . . . . . . . . . . 12 7.2.11 overvoltage protection (vosense pin) . . . . . . . . . . . . . . . . . . . . . . . 12 7.2.12 pfc open-loop protection (vosense pin) . . . . . . . . . . . . . . . . . . . . . . . 13 7.2.13 driver (pfcdriver pin). . . . . . . . . . . . . . . . . . . . . . 13 7.3 flyback controller . . . . . . . . . . . . . . . . . . . . . . 13 7.3.1 multimode operation . . . . . . . . . . . . . . . . . . . . 13 7.3.2 valley switching (hv pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.3.3 current mode control (fbsense pin) . . . . . . . . . . . . . . . . . . . . . . . 15 7.3.4 demagnetization (fbaux pin). . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.3.5 flyback control/time-out (fbctrl pin). . . . . . . . . . . . . . . . . . . . . . . . . 16 7.3.6 soft start-up (fbsense pin) . . . . . . . . . . . . . 17 7.3.7 maximum on-time . . . . . . . . . . . . . . . . . . . . . 18 7.3.8 overvoltage protection (fbaux pin). . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.3.9 overcurrent protection (fbsense pin) . . . . . . . . . . . . . . . . . . . . . . . 19 7.3.10 overpower protection. . . . . . . . . . . . . . . . . . . 19 7.3.11 driver (fbdriver pin) . . . . . . . . . . . . . . . . . 19 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 20 9 thermal characteristics . . . . . . . . . . . . . . . . . 21 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . 21 11 application information . . . . . . . . . . . . . . . . . 26 12 package outline. . . . . . . . . . . . . . . . . . . . . . . . 28 13 revision history . . . . . . . . . . . . . . . . . . . . . . . 29 14 legal information . . . . . . . . . . . . . . . . . . . . . . 30 14.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 30 14.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 14.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 30 14.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 31 15 contact information . . . . . . . . . . . . . . . . . . . . 31 16 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 |
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